Semiconductor devices typically comprise a plurality of components formed by photolithographic processes in a multilayered structure. The structure is supplied with signals typically via a sunburst pattern which makes electrical contact to lands on the semiconductor device. For completing the packaging of the device, the sunburst pattern is connected to external signal and power sources for the device to operate and the device is protected from the environment.
One attractive technology for completing the semiconductor package is termed a "Ball Grid Array" (BGA). The BGA comprises a planar component "carrier" which may comprise a rigid plastic layer with metallic (gold) islands or dots on the top surface. The dots are connected to lands on the bottom surface of the carrier by through connections which provide electrical continuity from the power and signal sources to the metallic dots. The BGA, thus, is employed as a support or carrier for the semiconductor device and as a medium for providing the requisite drive and signals to the attached semiconductor device.
The semiconductor device, accordingly, has to be connected to the carrier in a manner to permit electrical continuity. To this end, it is necessary to provide solder on top of each of the gold dots on the top surface of the carrier to bond the semiconductor securely in place. This has been accomplished typically by apparatus which places a pattern of tiny solder balls on top of the gold dots. U.S. Pat. No. 5,431,332 issued Jul. 11, 1995 and U.S. Pat. No. 5,551,216 issued Sep. 3, 1996 disclose techniques for the placement of such solder balls. Each of these patents discloses a technique where a tooling plate or stencil with an array of apertures, which matches the array of gold dots, is filled with tiny solder balls and is then juxtaposed with the carrier to transfer the balls to the carrier. The carrier has a coating of adhesive to hold the balls in place and the carrier is then heated to affix the balls permanently.
The apparatus to place the balls on the carrier is expensive and not sufficiently fast to meet present throughput requirements inexpensively. Further, the apparatus is not easily adapted to increasingly fine resolution to meet projected semiconductor packaging requirements. Also, solder balls are presently so small that they frequently become lodged in undesirable positions in the apparatus necessitating frequent inspection and down time.